DSC POWER 864 - REV2 Spezifikationen Seite 37

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Seitenansicht 36
© 2009 Microchip Technology Inc. Preliminary DS39927B-page 35
PIC24F16KA102 FAMILY
TABLE 4-17: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<15:0> xxxx
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000
RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<15:0> xxxx
RCFGCAL 0626 RTCEN
RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: DUAL COMPARATOR REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CMSTAT 0630 CMSIDL
C2EVT C1EVT
C2OUT C1OUT 0000
CVRCON 0632
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000
CM1CON 0634 CON COE CPOL CLPWR
CEVT COUT EVPOL1 EVPOL0 —CREF CCH1 CCH0 0000
CM2CON 0636 CON COE CPOL CLPWR
CEVT COUT EVPOL1 EVPOL0 —CREF CCH1 CCH0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: CRC REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CRCCON 0640
CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0040
CRCXOR 0642 X<15:1>
0000
CRCDAT 0644 CRC Data Input Register 0000
CRCWDAT 0646 CRC Result Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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